1. Field of the Invention
The present invention relates to a method for manufacturing a poly gate and a polycide gate, more particularly, to a method for simultaneously manufacturing and integrating a poly gate and a polycide gate of an integrated circuit onto a chip.
2. Description of the Related Art
With the technological advances in the electronic industry, the trend of electronic products moves toward integrating peripheral devices onto a chip. They originally needed a printed circuit board on which memory module chips are mounted and peripheral circuits are added. But now, with the upgrading in the design ability of electronic devices and in the processability of semiconductors, the memory and the peripheral devices are gradually being integrated onto a chip. Thus it brings the manufacturers of electronic products and consumers a more convenient and versatile choice, further stimulating and accelerating the advance of the electronic industry. For the semiconductor chip manufacturers, this trend of advance implies the challenge and promotion of technical ability.
Using an image chip as an example, in order to enhance the performance and resolution of images, each image must be resolved into more than one million pixels and then each pixel is memorized into a memory cell of a memory chip. At this time, the performance of the image chip expresses itself in two manners. Firstly, whether the memory cells on each pixel array can truly store potential signals representative of pixels. If the stored electronic signals fail to truly record pixels due to leakage, transmitted images are incorrect. A common phenomenon is that many spots appear on an image due to the leakage of storage signals of memory cells, resulting in a poor image. Secondly, the access speed of memory cells in the peripheral circuits integrated in the image chip must be fast enough to process large volumes of data in the pixel arrays.
Accordingly, memory cells on a chip must meet two requirements, one of which is that the current representing electronic signals can not be leaked, but the speed requirement is relatively not so high; the other is that a fast speed is required, and leakage is not the key point of requirement so long as it is within a certain limit.
Metal-oxide-semiconductor field-effect transistor (MOSFET) is the most important device in ultra large scale integrated circuits, whose structure includes a metal-oxide-semiconductor (MOS) capacitor with both the source and the drain positioned at both sides of the MOS capacitor and having electricity opposite to the silicon substrate, wherein the MOS capacitor comprises an uppermost metal portion known as a gate, an oxide layer beneath the gate, and a lowermost semiconductor, commonly a silicon substrate.
The uppermost metal portion of the MOS capacitor primarily comprises of polysilicon known as a poly gate. Sometimes there is a need for depositing a layer of silicide over the polysilicon since the resistivity of a polysilicon is not the lowest. The gate comprising polysilicon and silicide is referred to as a polycide gate.
The poly gate and the polycide gate individually meet the requirements above for leakage and access speed. The resistivity of the poly gate is not the lowest and the access speed thereof not the fastest, whereas its leakage is less serious. So that the poly gate is suitable as a component of the pixel array area where requires storing potential signals without leakage in an image chip. On the other hand, in contrast to the poly gate, the polycide gate is more likely to produce leakage. The polycide gate is suitable as a peripheral circuit of the image chip to meet the requirement of fast speed in favor of quickly processing large volumes of pixel data within the pixel array area because of its low resistivity, small RC time delay and fast device switching speed.
However, in order for simultaneously manufacturing the poly gate and the polycide gate on the silicon substrate, many derived process problems are left behind to be solved. These are the subject which the present invention intends to solve.
A process for simultaneously manufacturing a poly gate and a polycide gate integrated onto a chip of the prior art is shown from FIG. 1a to FIG. 1d. A poly gate is first produced in a poly gate region 1, including depositing a gate oxide layer 3 of an MOS capacitor, depositing a polysilicon 4 and through photolithographic and etching processes. The deposition layer on a polycide gate region 2 is etched cleanly to retain the original state, as shown in FIG. 1a. Subsequently a polycide gate is produced, including depositing a gate oxide layer 5, a polysilicon 6 and finally a silicide layer 7, and patterning a polycide gate photoresist 8 by the photolithographic process, as shown in FIG. 1b. After which the deposition layer other than covered by the polycide gate photoresist is removed to form a polycide gate 10, as shown in FIG. 1c. Finally, a gate spacer is prepared, as shown in FIG. 1d.
This is a straightforward method. In other words, since two different gates are required, one of which is first made and next the other one. The gate oxide layer and the polysilicon required are deposited twice. Problems derived therefrom include: firstly, the gate oxide layer must be deposited twice and etched twice; secondly, the polysilicon must also be deposited twice and etching is also carried out twice. It further induces the most serious third and fourth problems besides adding process burden, which are: thirdly, the second deposition of the polysilicon forms residues on the poly gate due to etching problems, resulting in a residual spacer 9, as shown in FIG. 1c; fourthly, the residual spacer makes the channel of the poly gate not easily controllable and also causes the poly gate spacer 11 not identical to the polycide gate spacer 12, as shown in FIG. 1d. Fifthly, the process window needs fine adjustment which may take more than one month. Not only this consumes time but also laborious. Sixthly, it causes top lost of the poly gate upon etching the second deposited polysilicon.
Briefly, the prior art first produces a poly gate and then a polycide gate. The first made poly gate suffers various problems caused by the course of producing the polycide gate, including deposition residual, overetching etc.